Basic Logic Gates

Think of logic gates as tiny digital decision-makers. They take binary inputs (0s and 1s) and perform specific logical operations on them to produce a binary output. These operations are the foundation of digital electronics, used in everything from computers to smartphones.

And Gate

One of the most important, easy and basic logic gates that is sewed into the souls of electronics engineers is the AND gate. If the Alphabet D had two legs on its flat side and a nose on the other, we could call the alphabet as an AND gate, but regardless I think we can still call AND gate as AND gate which is the two legged D.

So what does this gate actually do?

And gate could be called as the multiplication between two binary bits in a layman language. Here is the Truth Table of the AND gate AKA a table which has the outputs for all the possible inputs.

The and gate gives a high output when all the inputs are high, The company is happy when everyone is happy.

The And operation is read in many different ways. “A anded with B”, “A dot B”, or just “AB”. whatever comforts you. There are ways to denote the operation on paper, “A.B”, “A & B” or just “A and B”.

AND gate in VHDL

Let us write a VHDL code for the And gate in VIVADO. And is obviously an operation in HDLs. But right now let us focus on writing a gate so that it can be instantiated into different modules for modular design.

Declaring The Packages

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;

Declaring the Entity for the And Gate

Entity ANDGATE is
Port (A, B : in std_logic; Y : out std_logic);
End ANDGATE;

Behavioral Architecture of the And Gate

Architecture Behavioral of ANDGATE is
Begin

Whenever we are trying to write a behavioral code it is a good practice to use Process, although it might seem unnecessary at some stages. Good coding practices are always welcomed

Process(A,B)
Begin 
Y <= A and B;
end  Process;
end Behavioral;

Or Gate

Another Fundamental Gate which is the party animal of the gates. It goes high even if anyone is high. What a vibe catcher. Or gate looks as if someone punched the AND gate in the wrong place.

Functionality of The OR gate

Here is the truth table of the OR gate which actually defines what the OR gate does

So the Or gate gives output high when any of the inputs are high. It is called the orring operation or in a Layman language we can call it addition but if we observe the case when A and B are high if we are adding we should get 0 as the output and 1 as the carry as we don’t see that happening here we should be careful while we call it as addition as it is not completely true. It is better to address it as the OR operation.

OR gate in VHDL

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;

The regular Library Declaration where we use the package STD_LOGIC_1164 and we use ‘all’ the parts of the package.

Entity ORGATE is
Port( A, B : in std_logic; Y : out std_logic);
end ORGATE;

It is of course important to use the same name while ending the entity as the name is very significant to the entity.

We mention A and B as inputs of the data type std_logic and Y as the output of the OR gate of data type std_logic. All these data types of the ‘in’ and ‘out’ should be the same. Try experimenting with different data types to find the red line below them which shouts error.

Architecture Behavioral of ORGATE is
Begin
process(A, B)
Begin
Y <= A or B;
End process;
End Behavioral;

Again OR operation is just an operation but knowing how to make it into a component is essential for modular or hierarchical design that is used most frequently in Structural Designing.

Buffer

Buffer is just as it sounds, it just lets whatever the input it to become the output. But why do you need a gate to do the same? It surely could be done using a wire where the input just goes ahead to become the output on the other end. Buffer is actually used to introduce delay into a circuit. A delay is used in Synchronous circuits sometimes to time the circuits perfectly.

The symbol of the buffer is just a triangle with one input and one output.

Functionality of the Buffer Gate

The Truth Table of the Buffer is the most simple. Whatever is the input so is the output.

Buffer in VHDL

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;

Library Declaration Followed by Entity Declaration

Entity Buffer is
Port( A : in std_logic; B : out std_logic);
End Buffer;

The Architecture of Buffer should just ensure that the input and output are the same

Architecture Behavioral of Buffer is
Begin 
process(A)
Begin
B <= A ;
End process;
End Behavioral;

NOT Gate

Not gate is the pessimistic friend of the logic gate family where it negates every input, regardless if it is high or low i.e. 1 or 0. And the symbol of NOT gate is a buffer gate with a bubble in front of it.

Functionality of the NOT Gate

Truth Table

NOT gate in VHDL

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;


Entity NOTGATE is 
PORT( A : in std_logic; B : out std_logic);
End NOTGATE;


Architecture Behavioral of NOTGATE is
Begin 
process(A)
Begin
B <= not(A);
End process;
End Behavioral;

ESD Courses

AI COURSES

Passive income

Others